1m x 1 static ram cy7c107 cy7c1007 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 december 1992 ? revised september 3, 1999 features ? high speed ?t aa = 12 ns cmos for optimum speed/power low active power ?825 mw low standby power ?275 mw 2.0v data retention (optional) ? 100 w automatic power-down when deselected ttl-compatible inputs and outputs functional description the cy7c107 and cy7c1007 are high-performance cmos static rams organized as 1,048,576 words by 1 bit. easy memory expansion is provided by an active low chip enable (ce ) and three-state drivers. these devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected. writing to the devices is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the input pin (d in ) is written into the memory location specified on the ad- dress pins (a 0 through a 19 ). reading from the devices is accomplished by taking chip en- able (ce ) low while write enable (we ) remains high. under these conditions, the contents of the memory location speci- fied by the address pins will appear on the data output (d out ) pin. the output pin (d out ) is placed in a high-impedance state when the device is deselected (ce high) or during a write operation (ce and we low). the cy7c107 is available in a standard 400-mil-wide soj; the cy7c1007 is available in a standard 300-mil-wide soj. logic block diagram pin configuration top view soj 512x2048 arra y a 5 a 6 a 7 column decoder row decoder sense amps power down we ce input buffer d out d in a 4 a 3 a 2 a 1 a 0 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 12 13 25 28 27 26 gnd a 11 a 12 a 13 a 14 we v cc a 9 a 10 ce a 0 d out d in a 8 a 7 a 6 a 2 a 1 a 4 nc nc a 15 a 16 a 8 a 12 a 14 a 16 a 15 a 10 a 11 a 13 a 17 a 18 a 19 a 17 a 18 a 19 a 5 a 3 a 9 107-1 107-2 selection guide 7c107-12 7c1007-12 7c107-15 7c1007-15 7c107-20 7c1007-20 7c107-25 7c1007-25 7c107-35 maximum access time (ns) 12 15 20 25 35 maximum operating current (ma) 150 135 125 120 110 maximum standby current (ma) 50 40 30 30 25
cy7c107 cy7c1007 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage on v cc relative to gnd [1] .....? 0.5v to +7.0v dc voltage applied to outputs in high z state [1] ....................................... ? 0.5v to v cc + 0.5v dc input voltage [1] .................................... ? 0.5v to v cc + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma notes: 1. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. t a is the ? instant on ? case temperature. 3. not more than 1 output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. operating range range ambient temperature [2] v cc commercial 0 c to +70 c 5v 10% industrial ? 40 c to +85 c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c107-12 7c1007-12 7c107-15 7c1007-15 7c107-20 7c1007-20 min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 v i ix input load current gnd < v i < v cc ? 1+1 ? 1+1 ? 1+1 a i oz output leakage current gnd < v i < v cc , output disabled ? 5+5 ? 5+5 ? 5+5 a i os output short circuit current [3] v cc = max., v out = gnd ? 300 ? 300 ? 300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 150 135 125 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 50 40 30 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = 0 222ma
cy7c107 cy7c1007 3 electrical characteristics over the operating range (continued) parameter description test conditions 7c107-25 7c1007-25 7c107-35 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ? 0.3 0.8 ? 0.3 0.8 v i ix input load current gnd < v i < v cc ? 1+1 ? 1+1 a i oz output leakage current gnd < v i < v cc , output disabled ? 5+5 ? 5+5 a i os output short circuit current [3] v cc = max., v out = gnd ? 300 ? 300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 120 110 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 25 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = 0 22ma capacitance [4] parameter description test conditions max. unit c in : addresses input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 7pf c in : controls 10 pf c out output capacitance 10 pf note: 4. tested initially and after any design or process changes that may affect these parameters.
cy7c107 cy7c1007 4 ac test loads and waveforms 3.0v 5v output r1 480 ? r2 255 ? 30 pf including jig and scope gnd 90% 10% 90% 10% 3 ns 3 ns 5v output 5pf including jig and scope (a) (b) output 1.73v equivalentto: th venin equivalent all input pulses r2 255 ? r1 480 ? 167 ? 107-3 107-4 switching characteristics [5] over the operating range 7c107-12 7c1007-12 7c107-15 7c1007-15 7c107-20 7c1007-20 7c107-25 7c1007-25 7c107-35 parameter description min. max. min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 12 15 20 25 35 ns t aa address to data valid 1215202535ns t oha data hold from address change 33333ns t ace ce low to data valid 1215202535ns t lzce ce low to low z [6] 33333ns t hzce ce high to high z [6, 7] 6781010ns t pu ce low to power-up 0 0 0 0 0 ns t pd ce high to power-down 12 15 20 25 35 ns write cycle [8] t wc write cycle time 12 15 20 25 35 ns t sce ce low to write end1012152025 ns t aw address set-up to write end 10 12 15 20 25 ns t ha address hold from write end 00000ns t sa address set-up to write start 00000ns t pwe we pulse width 1012152025 ns t sd data set-up to write end 7 8 10 15 20 ns t hd data hold from write end 0 0 0 0 0 ns t lzwe we high to low z [6] 33333ns t hzwe we low to high z [6, 7] 6781010ns notes: 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe for any given device. 7. t hzce and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write.
cy7c107 cy7c1007 5 data retention characteristics over the operating range (l version only) parameter description conditions [9] min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3 or v in < 0.3v 50 a t cdr [4] chip deselect to data retention time 0 ns t r [4] operation recovery time t rc ns data retention waveform 4.5v 4.5v ce v cc t cdr v dr > 2v data retention mode t r 107-5 switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 [11, 12] notes: 9. no input may exceed v cc + 0.5v. 10. device is continuously selected, ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha 107-6 address data out 50% 50% data valid t rc t ace t lzce t pu high impedance t hzce t pd high icc isb impedance address ce data out v cc supply current 107-7
cy7c107 cy7c1007 6 write cycle no. 1 (ce controlled) [13] write cycle no. 2 (we controlled) [13] note: 13. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) data valid t sce t aw t sa t pwe t ha t hd t sd t wc high impedance address ce we data out data in 107-8 t wc data valid data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd address ce we data out data in 107-9
cy7c107 cy7c1007 7 truth table ce we d out mode power h x high z power-down standby (i sb ) l h data out read active (i cc ) l l high z write active (i cc ) ordering information speed (ns) ordering code package name package type operating range 12 cy7c107-12vc v28 28-lead (400-mil) molded soj commercial cy7c1007-12vc v21 28-lead (300-mil) molded soj 15 cy7c107-15vc v28 28-lead (400-mil) molded soj commercial cy7c1007-15vc v21 28-lead (300-mil) molded soj 15 CY7C107-15VI v28 28-lead (400-mil) molded soj industrial cy7c1007-15vi v21 28-lead (300-mil) molded soj 20 cy7c107-20vc v28 28-lead (400-mil) molded soj commercial cy7c1007-20vc v21 28-lead (300-mil) molded soj 25 cy7c107-25vc v28 28-lead (400-mil) molded soj commercial cy7c1007-25vc v21 28-lead (300-mil) molded soj contact factory for ? l ? version availability. document #: 38-00232-c package diagrams 28-lead (300-mil) molded soj v21 51-85031-b
cy7c107 cy7c1007 ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-lead (400-mil) molded soj v28 51-85032-a
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